The present invention relates generally to power amplifiers, in particular, to microwave power amplifiers and, more particularly to an improved monolithic microwave integrated circuit (MMIC) power amplifier.
Increasing the power output in power amplifiers, such as monolithic microwave integrated circuit (MMIC) power amplifiers, typically requires increasing the number of FETs (field effect transistors) or, in particular applications, the number of Bipolar-type devices. Including more FETs typically requires a larger MMIC die size due to the arrangement of the FETs on the die and requirements of the combiner and divider networks. However, larger MMIC die are more expensive as cost is approximately proportional to die size. Thus, smaller MMIC die size is more desirable because of reduced cost.
Various attempts have been proposed to reduce the die size of power amplifiers, such as that disclosed by Tserng, U.S. Pat. No. 5,519,358. Tserng proposes a xe2x80x9cfolded FETxe2x80x9d configuration to pack the transistors into a compact area. However, Tserng does not allow for symmetric dividers and combiners for an even mode operation of the transistors.
Buer et al., U.S. Pat. No. 5,952,886, attempts to overcome some of the problems of Tserng and proposes a diagonally orientated FET configuration. Buer et al. discloses that the xe2x80x9cstaggeredxe2x80x9d FET arrangement permits more FETs to be placed across the MMIC chip than a xe2x80x9cstack-upxe2x80x9d configuration. In addition, Buer et al. discloses multiple matching and combiner networks for even mode operation. However, the staggered configuration of Buer et al. increases the design time and difficulty due to the precise FET overlap angles needed for optimum performance. In addition, Buer et al. provides for matching circuitry on only one side of the FET arrangement, thereby decreasing matching circuit effectiveness as well as performance and increasing the risk of oscillation. Furthermore, Buer et al. includes a wide bias interconnection loop in the center of the chip to deal with inherent geometry problems associated with injecting bias current in the configuration. This additional circuitry can take valuable space on the die which is generally not desirable.
Accordingly, there exists a need for a high power MMIC amplifier that reduces the die size. In addition, there is a need for a lower cost power amplifier. Further, there is a need for an improved performance power amplifier having higher output power, higher gain and increased efficiency.
The present invention overcomes the problems outlined above and provides an improved power amplifier. In particular, the present invention provides a MIMIC power amplifier with an improved FET geometry. More particularly, the present invention provides a MIMIC power amplifier with a folded configuration, improved performance, reduced number of combining circuits, and reduced die size.
In accordance with one embodiment of the present invention, a microwave power amplifier includes a plurality of FETs in a folded configuration having shared inputs and outputs.
In accordance with another embodiment of the present invention, a microwave power amplifier includes a plurality of FETs arranged to form one or more sections. Multiple sections are arranged in a folded amplifier configuration.